Metal semiconductor field effect transistors (MESFETs) integrated with heterojunction bipolar transistors (HBTs) on the same III-V semiconductor chip extend the capability of HBT circuits by providing: (1) high input impedance for amplifiers and sample-and-hold circuits; (2) low noise front ends; (3) active loads, which are particularly important in low power circuits: (4) current sources and sinks; and (5) low power random access memory (RAM) cells. Demonstrations of HBT-FET integration reported in the prior art have employed complex processes involving stacked structures and/or multiple epitaxial growths. At the present time, these processes have not advanced to actual circuit applications.
Prior art HBT-FET circuits formed by multilayer or selective area growth place severe demands on both material growth and device fabrication. Multilayer growth processes generally form non-planar devices. Conventional planar processes require a selective area regrowth of MESFET material on prepatterned HBT wafers. This regrowth of material requires additional processing steps and sophisticated cleaning procedures that lead to low yield and high cost fabrication. Thus there is a need for a planar III-V semiconductor structure that can be fabricated easily and inexpensively to provide the benefits of HBT-FET integration.